1. Field
The present disclosure is directed to a sigma-delta modulator and, more specifically, to techniques for delay compensation of continuous-time sigma-delta modulators.
2. Related Art
Broadly, sigma-delta modulation refers to a technique for encoding high resolution signals into lower resolution signals using pulse-code modulation. Sigma-delta modulation is increasingly employed in a wide range of electronic components, e.g., digital-to-analog converters (DACs), analog-to-digital converters (ADCs), frequency synthesizers, switch-mode power supplies, and motor controls. A DAC or ADC that implements sigma-delta modulation can achieve relatively high resolution while being manufactured using low-cost complementary metal-oxide semiconductor (CMOS) processes.
Compensatory feedback for a continuous-time sigma-delta modulator has traditionally been implemented in the analog domain (i.e., prior to quantization) or in the digital domain (i.e., subsequent to quantization). Unfortunately, continuous-time sigma-delta architectures that implement compensatory feedback in the analog domain are usually limited by analog summer performance, due to the fact that the analog summer is required to sum high frequency digital with nominally low frequency analog. Moreover, higher digital clock frequencies impose larger bandwidth requirements on an analog summer. As such, applying compensatory feedback in the analog domain (i.e., prior to quantization) requires a relatively expensive analog summer.
With reference to FIG. 1, a block diagram of a relevant portion of a conventional continuous-time sigma-delta modulator 100, that implements delay compensation in the analog domain, is illustrated. As is shown in FIG. 1, the modulator 100 includes an analog loop filter block 102 that receives an analog input signal and a standard digital feedback signal. The block 102 provides one or more analog outputs (depending on an analog loop filter implementation) to one or more respective inputs of an analog summer 104. Another input of the analog summer 104 receives (from a compensation block 108) a compensatory digital feedback signal D1 (which includes n-bits). The analog summer 104 sums the input signals and provides an analog output signal to an input of a quantizer 106, which provides an n-bit digital output signal that represents the analog input signal.
As is shown in FIG. 1, a compensatory feedback path includes the compensation block 108, which delays a digital output signal by ‘k’ time delays and scales the digital output signal by a weighting factor ak. Similarly, a standard feedback path includes a feedback block 110, which delays a digital output signal by ‘j’ time delays and scales the digital output signal by a weighting factor bj. The blocks 108 and 110 may also be configured to sum multiple delayed scaled digital output signals. As noted above, higher digital clock frequencies for the feedback signal D1 impose relatively large bandwidth requirements on the analog summer 104 and, as such, require a relatively high performance analog summer.
An example of a continuous-time sigma-delta modulator that implements delay compensation (compensatory feedback) entirely in the digital domain (i.e., subsequent to quantization) is disclosed in U.S. Patent Application Publication No. 2005/0068213 (hereinafter “the '213 application”), assigned to Texas Instruments Incorporated. However, employing the approach disclosed in the '213 application also has drawbacks, as it may be difficult to align digital levels with analog levels (as a digital step size does not generally match analog levels) and the approach is generally impractical for continuous-time sigma-delta modulators that employ quantizers that provide a small number of bits (e.g., two or fewer bits).
With reference to FIG. 2, a block diagram of a relevant portion of a conventional continuous-time sigma-delta modulator 200, that implements delay compensation in the digital domain, is illustrated. As is shown in FIG. 2, the modulator 200 includes an analog loop filter block 202 that receives an analog input signal and a standard digital feedback signal. The block 202 provides one or more analog output signals (depending on the analog loop filter implementation) to one or more respective inputs of an analog summer 204. The analog summer 204 sums the analog output signals and provides a summed analog signal to an input of an n-bit quantizer 206. The quantizer 206 provides an n-bit digital output signal (that is representative of a level of the analog input signal) to respective inputs of digital summer 208.
As is shown in FIG. 2, a compensatory feedback path includes a compensation block 210 that delays an n-bit digital output signal by ‘k’ time delays and scales the digital output signal by a weighting factor ak. A compensatory digital feedback signal D2 (which includes n-bits) is provided (from the block 210) to another input of the digital summer 208. The digital summer 208 sums the inputs received from outputs of the quantizer 206 and the block 210 to provide the n-bit digital output signal. Similarly, a standard feedback path includes a feedback block 212 that delays the digital output signal by ‘j’ time delays and scales the digital output signal by a weighting factor bj. The blocks 210 and 212 may also be configured to sum multiple delayed scaled digital output signals. It should be appreciated that when the weighting factor ak is a non-integer, the number of new analog levels that require generation increases (e.g., when the weighting factor ak is equal to 0.1, ten times more analog levels require generation). As noted above, as it is difficult to align digital levels with analog levels (as digital step size does not generally match analog levels), the approach is generally impractical for continuous-time sigma-delta modulators that employ quantizers that provide a small number of bits (e.g., two or fewer bits).